Les registres TIMER

publication: 29 décembre 2021 / mis à jour 29 décembre 2021

Résumé des registres

Name	Description	TIMG0	TIMG1	Acc
Timer 0 configuration and control registers
TIMGn_T0CONFIG_REG	Timer 0 configuration register	$3FF5F000	$3FF60000	R/W
TIMGn_T0LO_REG	Timer 0 current value, low 32 bits	$3FF5F004	$3FF60004	RO
TIMGn_T0HI_REG	Timer 0 current value, high 32 bits	$3FF5F008	$3FF60008	RO
TIMGn_T0UPDATE_REG	Write to copy current timer value to TIMGn_T0_(LO/HI)_REG	$3FF5F00C	$3FF6000C	WO
TIMGn_T0ALARMLO_REG	Timer 0 alarm value, low 32 bits	$3FF5F010	$3FF60010	R/W
TIMGn_T0ALARMHI_REG	Timer 0 alarm value, high bits	$3FF5F014	$3FF60014	R/W
TIMGn_T0LOADLO_REG	Timer 0 reload value, low 32 bits	$3FF5F018	$3FF60018	R/W
TIMGn_T0LOAD_REG	Write to reload timer from TIMGn_T0_(LOADLOLOADHI)_REG	$3FF5F020	$3FF60020	WO
Timer 1 configuration and control registers
TIMGn_T1CONFIG_REG	Timer 1 configuration register	$3FF5F024	$3FF60024	R/W
TIMGn_T1LO_REG	Timer 1 current value, low 32 bits	$3FF5F028	$3FF60028	RO
TIMGn_T1HI_REG	Timer 1 current value, high 32 bits	$3FF5F02C	$3FF6002C	RO
TIMGn_T1UPDATE_REG	Write to copy current timer value to TIMGn_T1_(LO/HI)_REG	$3FF5F030	$3FF60030	WO
TIMGn_T1ALARMLO_REG	Timer 1 alarm value, low 32 bits	$3FF5F034	$3FF60034	R/W
TIMGn_T1ALARMHI_REG	Timer 1 alarm value, high 32 bits	$3FF5F038	$3FF60038	R/W
TIMGn_T1LOADLO_REG	Timer 1 reload value, low 32 bits	$3FF5F03C	$3FF6003C	R/W
TIMGn_T1LOAD_REG	Write to reload timer from TIMGn_T1_(LOADLOLOADHI)_REG	$3FF5F044	$3FF60044	WO
System watchdog timer configuration and control registers
TIMGn_Tx_WDTCONFIG0_REG	Watchdog timer configuration register	$3FF5F048	$3FF60048	R/W
TIMGn_Tx_WDTCONFIG1_REG	Watchdog timer prescaler register	$3FF5F04C	$3FF6004C	R/W
TIMGn_Tx_WDTCONFIG2_REG	Watchdog timer stage 0 timeout value	$3FF5F050	$3FF60050	R/W
TIMGn_Tx_WDTCONFIG3_REG	Watchdog timer stage 1 timeout value	$3FF5F054	$3FF60054	R/W
TIMGn_Tx_WDTCONFIG4_REG	Watchdog timer stage 2 timeout value	$3FF5F058	$3FF60058	R/W
TIMGn_Tx_WDTCONFIG5_REG	Watchdog timer stage 3 timeout value	$3FF5F05C	$3FF6005C	R/W
TIMGn_Tx_WDTFEED_REG	Write to feed the watchdog timer	$3FF5F060	$3FF60060	WO
TIMGn_Tx_WDTWPROTECT_REG	Watchdog write protect register	$3FF5F064	$3FF60064	R/W
Configuration and Control Register for RTC CALI
TIMGn_RTCCALICFG_REG	RTC calibration configuration register	$3FF5F068	$3FF60068	varies
TIMGn_RTCCALICFG1_REG	RTC calibration configuration register 1	$3FF5F06C	$3FF6006C	RO
Interrupt registers
TIMGn_Tx_INT_ENA_REG	Interrupt enable bits	$3FF5F098	$3FF60098	R/W
TIMGn_Tx_INT_RAW_REG	Raw interrupt status	$3FF5F09C	$3FF6009C	RO
TIMGn_Tx_INT_ST_REG	Masked interrupt status	$3FF5F0A0	$3FF600A0	RO
TIMGn_Tx_INT_CLR_REG	Interrupt clear bits	$3FF5F0A4	$3FF600A4	WO

TIMGn_T0CONFIG_REG

\  31 30 29 28                                                 13 12 11 10   
\ |__|__|__|_____________________________________________________|__|__|__|__ 
 
$3ff5f000 constant TIMG_BASE 
: TIMGn_T0CONFIG_REG ( n -- a )  
    $10000 * TIMG_BASE + ;

bit 31: TIMGn_Tx_EN Lorsqu'il est défini, le compteur de base de temps timer x est activé. (R/W);
bit 30: TIMGn_Tx_INCREASE Lorsqu'il est défini, le compteur de la base de temps timer x incrémentera chaque tick d'horloge. Lorsqu'il est effacé, le compteur timer x base de temps décrémentera. (R/W);
bit 29: TIMGn_Tx_AUTORELOAD Lorsqu'il est réglé, le rechargement automatique de la minuterie x à l'alarme est activé. (R/W);
bit 28-13: TIMGn_Tx_DIVIDER Valeur de pré-échelle Timer x clock (Tx_clk).(R/W);
bit 12: TIMGn_Tx_EDGE_INT_EN Lorsqu'elle est définie, une alarme génère une interruption de type front. (R/W);
bit 11: TIMGn_Tx_LEVEL_INT_EN Lorsqu'elle est définie, une alarme génère une interruption de type niveau. (R/W);
bit 10: TIMGn_Tx_ALARM_EN Lorsqu'elle est définie, l'alarme est activée. Ce bit est automatiquement effacé une fois par l'alarme se déclenche. (R/W);

18 Timer Group (TIMG) 18.1 Introduction There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers based on 16-bit prescalers and 64-bit auto-reload-capable up/downcounters. The ESP32 contains two timer modules, each containing two timers. The two timers in a block are indicated by an x in TIMGn_Tx; the blocks themselves are indicated by an n. The timers feature: • A 16-bit clock prescaler, from 2 to 65536 • A 64-bit time-base counter • Configurable up/down time-base counter: incrementing or decrementing • Halt and resume of time-base counter • Auto-reload at alarm • Software-controlled instant reload • Level and edge interrupt generation 18.2 Functional Description 18.2.1 16bit Prescaler Each timer uses the APB clock (APB_CLK, normally 80 MHz) as the basic clock. This clock is then divided down by a 16-bit precaler which generates the time-base counter clock (TB_clk). Every cycle of TB_clk causes the timebase counter to increment or decrement by one. The timer must be disabled (TIMGn_Tx_EN is cleared) before changing the prescaler divisor which is configured by TIMGn_Tx_DIVIDER register; changing it on an enabled timer can lead to unpredictable results. The prescaler can divide the APB clock by a factor from 2 to 65536. Specifically, when TIMGn_Tx_DIVIDER is either 1 or 2, the clock divisor is 2; when TIMGn_Tx_DIVIDER is 0, the clock divisor is 65536. Any other value will cause the clock to be divided by exactly that value. 18.2.2 64bit Timebase Counter The 64-bit time-base counter can be configured to count either up or down, depending on whether TIMGn_Tx_ INCREASE is set or cleared, respectively. It supports both auto-reload and software instant reload. An alarm event can be set when the counter reaches a value specified by the software. Counting can be enabled and disabled by setting and clearing TIMGn_Tx_EN. Clearing this bit essentially freezes the counter, causing it to neither count up nor count down; instead, it retains its value until TIMGn_Tx_EN is set again. Reloading the counter when TIMGn_Tx_EN is cleared will change its value, but counting will not be resumed until TIMGn_Tx_EN is set. Software can set a new counter value by setting registers TIMGn_Tx_LOAD_LO and TIMGn_Tx_LOAD_HI to the intended new value. The hardware will ignore these register settings until a reload; a reload will cause the contents of these registers to be copied to the counter itself. A reload event can be triggered by an alarm (auto-reload at alarm) or by software (software instant reload). To enable auto-reload at alarm, the register TIMGn_Tx_AUTORELOAD should be set. If auto-reload at alarm is not enabled, the time-base counter will continue incrementing or decrementing after the alarm. To trigger a software instant reload, any value can be written to the register TIMGn_Tx_ LOAD_REG; this will cause the counter value to change instantly. Software can also change the direction of the time-base counter instantly by changing the value of TIMGn_Tx_INCREASE. The time-base counter can also be read by software, but because the counter is 64-bit, the CPU can only get the value as two 32-bit values, the counter value needs to be latched onto TIMGn_TxLO_REG and TIMGn_TxHI_REG first. This is done by writing any value to TIMGn_TxUPDATE_REG; this will instantly latch the 64-bit timer value onto the two registers. Software can then read them at any point in time. This approach stops the timer value being read erroneously when a carry-over happens between reading the low and high word of the timer value. 18.2.3 Alarm Generation The timer can trigger an alarm, which can cause a reload and/or an interrupt to occur. The alarm is triggered when the alarm registers TIMGn_Tx_ALARMLO_REG and TIMGn_Tx_ALARMHI_REG match the current timer value. In order to simplify the scenario where these registers are set ’too late’ and the counter has already passed these values, the alarm also triggers when the current timer value is higher (for an up-counting timer) or lower (for a down-counting timer) than the current alarm value: if this is the case, the alarm will be triggered immediately upon loading the alarm registers. The timer alarm enable bit is automatically cleared once an alarm occurs. 18.2.4 MWDT Each timer module also contains a Main System Watchdog Timer and its associated registers. While these registers are described here, their functional description can be found in the chapter entitled Watchdog Timer. 18.2.5 Interrupts • TIMGn_Tx_INT_WDT_INT: Generated when a watchdog timer interrupt stage times out. • TIMGn_Tx_INT_T1_INT: An alarm event on timer 1 generates this interrupt. • TIMGn_Tx_INT_T0_INT: An alarm event on timer 0 generates this interrupt. 18.3 Register Summary Name Description TIMG0 TIMG1 Acc Timer 0 configuration and control registers TIMGn_T0CONFIG_REG Timer 0 configuration register 0x3FF5F000 0x3FF60000 R/W TIMGn_T0LO_REG Timer 0 current value, low 32 bits 0x3FF5F004 0x3FF60004 RO TIMGn_T0HI_REG Timer 0 current value, high 32 bits 0x3FF5F008 0x3FF60008 RO TIMGn_T0UPDATE_REG Write to copy current timer value to TIMGn_T0_(LO/HI)_REG 0x3FF5F00C 0x3FF6000C WO TIMGn_T0ALARMLO_REG Timer 0 alarm value, low 32 bits 0x3FF5F010 0x3FF60010 R/W TIMGn_T0ALARMHI_REG Timer 0 alarm value, high bits 0x3FF5F014 0x3FF60014 R/W TIMGn_T0LOADLO_REG Timer 0 reload value, low 32 bits 0x3FF5F018 0x3FF60018 R/W TIMGn_T0LOAD_REG Write to reload timer from TIMGn_T0_(LOADLOLOADHI)_REG 0x3FF5F020 0x3FF60020 WO Timer 1 configuration and control registers TIMGn_T1CONFIG_REG Timer 1 configuration register 0x3FF5F024 0x3FF60024 R/W TIMGn_T1LO_REG Timer 1 current value, low 32 bits 0x3FF5F028 0x3FF60028 RO TIMGn_T1HI_REG Timer 1 current value, high 32 bits 0x3FF5F02C 0x3FF6002C RO TIMGn_T1UPDATE_REG Write to copy current timer value to TIMGn_T1_(LO/HI)_REG 0x3FF5F030 0x3FF60030 WO TIMGn_T1ALARMLO_REG Timer 1 alarm value, low 32 bits 0x3FF5F034 0x3FF60034 R/W TIMGn_T1ALARMHI_REG Timer 1 alarm value, high 32 bits 0x3FF5F038 0x3FF60038 R/W TIMGn_T1LOADLO_REG Timer 1 reload value, low 32 bits 0x3FF5F03C 0x3FF6003C R/W TIMGn_T1LOAD_REG Write to reload timer from TIMGn_T1_(LOADLOLOADHI)_REG 0x3FF5F044 0x3FF60044 WO System watchdog timer configuration and control registers TIMGn_Tx_WDTCONFIG0_REG Watchdog timer configuration register 0x3FF5F048 0x3FF60048 R/W TIMGn_Tx_WDTCONFIG1_REG Watchdog timer prescaler register 0x3FF5F04C 0x3FF6004C R/W TIMGn_Tx_WDTCONFIG2_REG Watchdog timer stage 0 timeout value 0x3FF5F050 0x3FF60050 R/W TIMGn_Tx_WDTCONFIG3_REG Watchdog timer stage 1 timeout value 0x3FF5F054 0x3FF60054 R/W TIMGn_Tx_WDTCONFIG4_REG Watchdog timer stage 2 timeout value 0x3FF5F058 0x3FF60058 R/W TIMGn_Tx_WDTCONFIG5_REG Watchdog timer stage 3 timeout value 0x3FF5F05C 0x3FF6005C R/W TIMGn_Tx_WDTFEED_REG Write to feed the watchdog timer 0x3FF5F060 0x3FF60060 WO TIMGn_Tx_WDTWPROTECT_REG Watchdog write protect register 0x3FF5F064 0x3FF60064 R/W Configuration and Control Register for RTC CALI TIMGn_RTCCALICFG_REG RTC calibration configuration register 0x3FF5F068 0x3FF60068 varies TIMGn_RTCCALICFG1_REG RTC calibration configuration register 1 Interrupt registers T

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