Le contrôleur SPI
publication: 10 mars 2022 / mis à jour 30 mars 2022
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Aperçu
Comme le montre la figure 1, ESP32 intègre quatre contrôleurs SPI qui peuvent être utilisés pour communiquer avec des périphériques utilisant le protocole SPI. Le contrôleur SPI0 est utilisé comme tampon pour accéder à la mémoire externe. Le contrôleur SPI1 peut être utilisé comme maître. Les contrôleurs SPI2 et SPI3 peuvent être configurés en tant que maître ou esclave. Quand il est utilisé comme maître, chaque contrôleur SPI peut piloter plusieurs signaux CS (CS0 ~ CS2) pour activer plusieurs esclaves. Les contrôleurs SPI1 ~ SPI3 partagent deux canaux DMA.
Les bus de signaux SPI sont constitués de signaux D, Q, CS0-CS2, CLK, WP et HD, comme le montre le tableau 1. Les contrôleurs SPI0 et SPI1 partagent un bus de signal via un arbitre: les signaux du bus partagé commencent par "SPI". Les contrôleurs SPI2 et SPI3 utilisent des bus de signal commençant respectivement par "HSPI" et "VSPI". Les lignes d'E/S incluses dans les bus de signaux peuvent être mappés sur des broches via le module IO_MUX ou la matrice GPIO.
Le contrôleur SPI prend en charge la communication en duplex intégral/semi-duplex à quatre lignes (lignes MOSI, MISO, CS et CLK) et communication semi-duplex à trois lignes uniquement (lignes DATA, CS et CLK) en mode GP-SPI. En mode QSPI, un SPI le contrôleur accède au flash ou à la SRAM en utilisant les bus de signal D, Q, CS0 ~ CS2, CLK, WP et HD en tant que quatre bits bus SPI parallèle. Le mappage entre les signaux de bus SPI et les signaux de fonction de broche sous différentes communications mode est indiqué dans le tableau 1.
| Four-line GP-SPI Full-duplex/half- duplex signal bus |
Three-line GP-SPI Half-duplex signal bus |
QSPI Pin Signal bus | Pin function signals | ||
|---|---|---|---|---|---|
| SPI signal bus | HSPI signal bus | VSPI signal bus | |||
| MOSI | DATA | D | SPID | HSPID | VSPID |
| MISO | - | Q | SPIQ | HSPIQ | VSPIQ |
| CS | CS | CS | SPICS0 | HSPICS0 | VSPICS0 |
| CLK | CLK | CLK | SPICLK | HSPICLK | VSPICLK |
| - | - | WP | SPIWP | HSPIWP | VSPIWP |
| - | - | HD | SPIHD | HSPIHD | VSPIHD |
Table 1. Mapping Between SPI Bus Signals and Pin Function Signals
Fonctionnalités SPI
SPI à usage général (GPSPI)
- Longueur de transfert de données programmable, en multiples de 1 octet
- Prise en charge de la communication full-duplex/half-duplex à quatre lignes et de la communication half-duplex à trois lignes
- Mode maître et mode esclave
- CPOL et CPHA programmables
- Horloge programmable
QSPI parallèle
- Prise en charge du format de communication pour des périphériques esclaves spécifiques tels que flash
- Format de communication programmable
- Six variantes d'opérations de lecture flash disponibles
- Passage automatique entre l'accès flash et SRAM
- États d'attente automatiques pour l'accès flash
Prise en charge SPI DMA
- Prise en charge de l'envoi et de la réception de données à l'aide de listes liées
Matériel d'interruption SPI
- Interruptions SPI
- Interruptions SPI DMA
GP-SPI
Le mode maître SPI prend en charge la communication en duplex intégral/semi-duplex à quatre lignes et la communication à trois lignes communication semi-duplex. La figure 2 décrit les connexions nécessaires pour quatre lignes communications en duplex intégral/semi-duplex.
The SPI1 ~ SPI3 controllers can communicate with other slaves as a standard SPI master. SPI2 and SPI3 can be configured as either a master or a slave. Every SPI master can be connected to three slaves at most by default. When not using DMA, the maximum length of data received/sent in one burst is 64 bytes. The data length is in multiples of one byte.
| Command | Description |
|---|---|
| 0x1 | Received by slave; writes data sent by the master into the slave status register via MOSI. |
| 0x2 | Received by slave; writes data sent by the master into the slave data buffer via MOSI. |
| 0x3 | Sent by slave; sends data in the slave buffer to master via MISO. |
| 0x4 | Sent by slave; sends data in the slave status register to master via MISO. |
| 0x6 | Writes master data on MOSI into data buffer and then sends the date in the slave data buffer to MISO. |
Table 2. Command Definitions Supported by GPSPI Slave in Halfduplex Mode
GPSPI Fourline Fullduplex Communication
When configured to four-line full-duplex mode, the ESP32 SPI can act as either a master or a slave. The length of received and sent data needs to be set by configuring the SPI_MISO_DLEN_REG, SPI_MOSI_DLEN_REG registers for master mode as well as SPI_SLV_RDBUF_DLEN_REG, SPI_SLV_WRBUF_DLEN_REG registers for slave mode. The SPI_DOUTDIN bit and SPI_USR_MOSI bit in register SPI_USER_REG should be configured to enable this communication mode. The SPI_USR bit in register SPI_CMD_REG needs to be configured to initialize a data transfer.
GPSPI Fourline Halfduplex Communication
When configured to four-line half-duplex mode, the ESP32 SPI can act as either a master or a slave. In this mode, the SPI communication supports flexible communication format as: command + address + dummy phase + received and/or sent data. The format is specified as follows:
- command: length of 0 ~ 16 bits; Master Out Slave In (MOSI)
- address: length of 0 ~ 32/64 bits; Master Out Slave In (MOSI)
- dummy phase: length of 0 ~ 256 SPI clocks
- received and/or sent data: length of 0 ~ 512 bits (64 bytes); Master Out Slave In (MOSI) or Master In Slave Out (MISO)
The address length is up to 32 bits in GP-SPI master mode and 64 bits in QSPI master mode. The command phase, address phase, dummy phase and received/sent data phase are controlled by bits SPI_USR_COMMAND, SPI_USR_ADDR, SPI_USR_DUMMY and SPI_USR_MISO/SPI_USR_MOSI respectively in register SPI_USER_REG. A certain phase is enabled only when its corresponding control bit is set to 1. Details can be found in register description. When SPI works as a master, the register can be configured by software as required to determine whether or not to enable a certain phase.
When SPI works as a slave, the communication format must contain command, address, received and/or sent data, among which the command has several options listed in Table 7-2. During data transmission or reception, the CS signal should keep logic level low. If the CS signal is pulled up during transmission, the internal state of the slave will be reset.
The master can write the slave status register SPI_SLV_WR_STATUS_REG, and decide whether to read data from register SPI_SLV_WR_STATUS_REG or register SPI_RD_STATUS_REG via the SPI_SLV_STATUS_READBACK bit in register SPI_SLAVE1_REG. The SPI master can maintain communication with the slave by reading and writing slave status register, thus realizing complex communication with ease.
The length of received and sent data is controlled by SPI_MISO_DLEN_REG and SPI_MOSI_DLEN_REG in master mode, as well as SPI_SLV_RDBUF_DLEN_REG and SPI_SLV_WRBUF_DLEN_REG in slave mode. A reception or transmission of data is controlled by bit SPI_USR_MOSI or SPI_USR_MISO in SPI_USER_REG. The SPI_USR bit in register SPI_CMD_REG needs to be configured to initialize a data transfer.
GP-SPI Threeline Halfduplex Communication
The three-line half-duplex communication differs from four-line half-duplex communication in that the reception and transmission shares one signal bus and that the communication format must contain command, address, received and/or sent data. Software can enable three-line half-duplex communication by configuring SPI_SIO bit in SPI_USER_REG register.
Note:
- In half-duplex communication, the order of command, address, received and/or sent data in the communication format should be followed strictly;
- In half-duplex communication, communication formats ”command + address + received data + sent data” and ”received data + sent data” are not applicable to DMA
- When ESP32 SPI acts as a slave, the master CS should be active at least one SPI clock period before a read/write process is initiated, and should be inactive at least one SPI clock period after the read/write process is completed.
GP-SPI Data Buffer
ESP32 SPI has 16 × 32 bits of data buffer to buffer data-send and data-receive operations. As is shown in Figure 7-3, received data is written from the low byte of SPI_W0_REG by default and the writing ends with SPI_W15_REG. If the data length is over 64 bytes, the extra part will be written from SPI_W0_REG.
Data buffer blocks SPI_W0_REG ~ SPI_W7_REG and SPI_W8_REG ~ SPI_W15_REG data correspond to the lower part and the higher part respectively. They can be used separately, and are controlled by the SPI_USR_MOSI_HIGHPART bit and the SPI_USR_MISO_HIGHPART bit in register SPI_USER_REG. For example, if SPI is configured as a master, when SPI_USR_MOSI_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for sending data; when SPI_USR_MISO_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for receiving data. If SPI acts as a slave, when SPI_USR_MOSI_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for receiving data; when SPI_USR_MISO_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for sending data.
Table 3. Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master
| Registers | mode0 | mode1 | mode2 | mode3 |
|---|---|---|---|---|
| SPI_CK_IDLE_EDGE | 0 | 0 | 1 | 1 |
| SPI_CK_OUT_EDGE | 0 | 1 | 1 | 0 |
| SPI_MISO_DELAY_MODE | 2(0) | 1(0) | 1(0) | 2(0) |
| SPI_MISO_DELAY_NUM | 0 | 0 | 0 | 0 |
| SPI_MOSI_DELAY_MODE | 0 | 0 | 0 | 0 |
| SPI_MOSI_DELAY_NUM | 0 | 0 | 0 | 0 |
GP-SPI Clock Control
The maximum output clock frequency of ESP32 GP-SPI master is fapb/2, and the maximum input clock frequency of the ESP32 GP-SPI slave is fapb/8. The master can derive other clock frequencies via frequency division.
SPI_CLKCNT_N and SPI_CLKDIV_PRE are two bits of register SPI_CLOCK_REG (Please refer to 7.7 Register Description for details). SPI_CLKCNT_H = ⌊ SPI_CLKCNT_N+1 –1⌋, SPI_CLKCNT_N=SPI_CLKCNT_L. When the SPI_CLK_EQU_SYSCLK bit in register SPI_CLOCK_REG is set to 1, and the other bits are set to 0, SPI output clock frequency is fapb. For other clock frequencies, SPI_CLK_EQU_SYSCLK needs to be 0. In slave mode, SPI_CLKCNT_N, SPI_CLKCNT_L, SPI_CLKCNT_H and SPI_CLKDIV_PRE should all be 0.
Polarité d'horloge GPSPI (CPOL) et phase d'horloge (CPHA)
La polarité d'horloge et la phase d'horloge de ESP32 SPI sont contrôlées par le bit SPI_CK_IDLE_EDGE dans le registre SPI_PIN_REG, Bit SPI_CK_OUT_EDGE et bit SPI_CK_I_EDGE dans le registre SPI_USER_REG, ainsi que SPI_MISO_DELAY_MODE[1:0] bit, SPI_MISO_DELAY_NUM[2:0] bit, SPI_MOSI_DELAY_MODE[1:0] bit, SPI_MOSI_DELAY_MUM[2:0] bit dans le registre SPI_CTRL2_REG. Le Tableau 7-3 et le Tableau 7-4 montrent la polarité et la phase de l'horloge ainsi que les enregistrer les valeurs pour ESP32 SPI maître et esclave, respectivement. Notez que pour mode0 et mode2 dans le Tableau 7-4, le les registres sont configurés différemment en mode non-DMA et en mode DMA, et que les données de l'esclave SPI sont sorties en avancer en mode DMA.
Table 4: Polarité et phase d'horloge et valeurs de registre SPI correspondantes pour l'esclave SPI
| Registers | mode0 | mode1 | mode2 | mode3 | ||
|---|---|---|---|---|---|---|
| Non-DMA | DMA | Non-DMA | DMA | |||
| SPI_CK_IDLE_EDGE | 1 | 0 | 1 | 0 | 1 | 0 |
| SPI_CK_I_EDGE | 0 | 1 | 1 | 1 | 0 | 0 |
| SPI_MISO_DELAY_MODE | 0 | 0 | 2 | 0 | 0 | 1 |
| SPI_MISO_DELAY_NUM | 0 | 2 | 0 | 0 | 2 | 0 |
| SPI_MOSI_DELAY_MODE | 2 | 0 | 0 | 1 | 0 | 0 |
| SPI_MOSI_DELAY_NUM | 2 | 3 | 0 | 2 | 3 | 0 |
- mode0 signifie CPOL=0, CPHA=0. Lorsque SPI est inactif, la sortie d'horloge est au niveau logique bas ; changements de données sur le front descendant de l'horloge SPI et est échantillonné sur le front montant ;
- mode1 signifie CPOL=0, CPHA=1. Lorsque SPI est inactif, la sortie d'horloge est au niveau logique bas ; changements de données à la hausse front de l'horloge SPI et est échantillonné sur le front descendant ;
- mode2 signifie quand CPOL=1, CPHA=0. Lorsque SPI est inactif, la sortie d'horloge est au niveau logique haut ; changements de données sur le front montant de l'horloge SPI et est échantillonné sur le front descendant ;
- mode3 signifie quand CPOL=1, CPHA=1. Lorsque SPI est inactif, la sortie d'horloge est au niveau logique haut ; changements de données sur le front descendant de l'horloge SPI et est échantillonné sur le front montant.
GP-SPI Timing
The data signals of ESP32 GP-SPI can be mapped to physical pins either via IO_MUX or via IO_MUX and GPIO matrix. Input signals will be delayed by two clkapb clock cycles when they pass through the matrix. Output signals will not be delayed.
When GP-SPI is used as master and the data signals are not received by the SPI controller via GPIO matrix, if GP-SPI output clock frequency is clkapb/2, register SPI_MISO_DELAY_MODE should be set to 0 when configuring the clock polarity. If GP-SPI output clock frequency is not higher than clkapb/4, register SPI_MISO_DELAY_MODE can be set to the corresponding value in Table 7-3 when configuring the clock polarity.
When GP-SPI is used in master mode and the data signals enter the SPI controller via the GPIO matrix:
- If GP-SPI output clock frequency is clkapb/2, register SPI_MISO_DELAY_MODE should be set to 0 and the dummy phase should be enabled (SPI_USR_DUMMY = 1) for one clkspi clock cycle (SPI_USR_DUMMY_CYCLELEN = 0) when configuring the clock polarity;
- If GP-SPI output clock frequency is clkapb/4, register SPI_MISO_DELAY_MODE should be set to 0 when configuring the clock polarity;
- If GP-SPI output clock frequency is not higher than clkapb/8, register SPI_MISO_DELAY_MODE can be set to the corresponding value in Table 7-3 when configuring the clock polarity
When GP-SPI is used in slave mode, the clock signal and the data signals should be routed to the SPI controller via the same path, i.e., neither the clock signal nor the data signals passes through GPIO matrix, or both of them pass through GPIO matrix. This is important in ensuring that the signals are not delayed by different time periods before they reach the SPI hardware.
To conclude, if signals do not pass through GPIO matrix, the SPI slave clock frequency is up to fapb/8; if signals pass through GPIO matrix, the SPI slave clock frequency is up to fapb/12. Note that (tspi/2–tpre) represents data output hold time for SPI slave in mode0 and mode2.
Register Summary
| Name | Description | SPI0 | SPI1 | SPI2 | SPI3 | Acc |
|---|---|---|---|---|---|---|
| Control and configuration registers | ||||||
| SPI_CTRL_REG | Bit order and QIO/DIO/QOUT/DOUT mode settings |
3FF43008 | 3FF42008 | 3FF64008 | 3FF65008 | R/W |
| SPI_CTRL2_REG | Timing configuration | 3FF43014 | 3FF42014 | 3FF64014 | 3FF65014 | R/W |
| SPI_CLOCK_REG | Clock configuration | 3FF43018 | 3FF42018 | 3FF64018 | 3FF65018 | R/W |
| SPI_PIN_REG | Polarity and CS configuration | 3FF43034 | 3FF42034 | 3FF64034 | 3FF65034 | R/W |
| Slave mode configuration registers | ||||||
| SPI_SLAVE_REG | Slave mode configuration and interrupt status | 3FF43038 | 3FF42038 | 3FF64038 | 3FF65038 | R/W |
| SPI_SLAVE1_REG | Slave data bit lengths | 3FF4303C | 3FF4203C | 3FF6403C | 3FF6503C | R/W |
| SPI_SLAVE2_REG | Dummy cycle length configuration | 3FF43040 | 3FF42040 | 3FF64040 | 3FF65040 | R/W |
| SPI_SLV_WR_STATUS_REG | Slave status/Part of lower master address | 3FF43030 | 3FF42030 | 3FF64030 | 3FF65030 | R/W |
| SPI_SLV_WRBUF_DLEN_REG | Write-buffer operation length | 3FF43048 | 3FF42048 | 3FF64048 | 3FF65048 | R/W |
| SPI_SLV_RDBUF_DLEN_REG | Read-buffer operation length | 3FF4304C | 3FF4204C | 3FF6404C | 3FF6504C | R/W |
| SPI_SLV_RD_BIT_REG | Read data operation length | 3FF43064 | 3FF42064 | 3FF64064 | 3FF65064 | R/W |
| User defined command mode registers | ||||||
| SPI_CMD_REG | Start user-defined command | 3FF43000 | 3FF42000 | 3FF64000 | 3FF65000 | R/W |
| SPI_ADDR_REG | Address data | 3FF43004 | 3FF42004 | 3FF64004 | 3FF65004 | R/W |
| SPI_USER_REG | User defined command configuration | 3FF4301C | 3FF4201C | 3FF6401C | 3FF6501C | R/W |
| SPI_USER1_REG | Address and dummy cycle configuration | 3FF43020 | 3FF42020 | 3FF64020 | 3FF65020 | R/W |
| SPI_USER2_REG | Command length and value configuration | 3FF43024 | 3FF42024 | 3FF64024 | 3FF65024 | R/W |
| SPI_MOSI_DLEN_REG | MOSI length | 3FF43028 | 3FF42028 | 3FF64028 | 3FF65028 | R/W |
| SPI_W0_REG | SPI data register 0 | 3FF43080 | 3FF42080 | 3FF64080 | 3FF65080 | R/W |
| SPI_W1_REG | SPI data register 1 | 3FF43084 | 3FF42084 | 3FF64084 | 3FF65084 | R/W |
| SPI_W2_REG | SPI data register 2 | 3FF43088 | 3FF42088 | 3FF64088 | 3FF65088 | R/W |
| SPI_W3_REG | SPI data register 3 | 3FF4308C | 3FF4208C | 3FF6408C | 3FF6508C | R/W |
| SPI_W4_REG | SPI data register 4 | 3FF43090 | 3FF42090 | 3FF64090 | 3FF65090 | R/W |
| SPI_W5_REG | SPI data register 5 | 3FF43094 | 3FF42094 | 3FF64094 | 3FF65094 | R/W |
| SPI_W6_REG | SPI data register 6 | 3FF43098 | 3FF42098 | 3FF64098 | 3FF65098 | R/W |
| SPI_W7_REG | SPI data register 7 | 3FF4309C | 3FF4209C | 3FF6409C | 3FF6509C | R/W |
| SPI_W8_REG | SPI data register 8 | 3FF430A0 | 3FF420A0 | 3FF640A0 | 3FF650A0 | R/W |
| SPI_W9_REG | SPI data register 9 | 3FF430A4 | 3FF420A4 | 3FF640A4 | 3FF650A4 | R/W |
| SPI_W10_REG SPI | data register 10 | 3FF430A8 | 3FF420A8 | 3FF640A8 | 3FF650A8 | R/W |
| SPI_W11_REG SPI | data register 11 | 3FF430AC | 3FF420AC | 3FF640AC | 3FF650AC | R/W |
| SPI_W12_REG SPI | data register 12 | 3FF430B0 | 3FF420B0 | 3FF640B0 | 3FF650B0 | R/W |
| SPI_W13_REG SPI | data register 13 | 3FF430B4 | 3FF420B4 | 3FF640B4 | 3FF650B4 | R/W |
| SPI_W14_REG SPI | data register 14 | 3FF430B8 | 3FF420B8 | 3FF640B8 | 3FF650B8 | R/W |
| SPI_W15_REG SPI | data register 15 | 3FF430BC | 3FF420BC | 3FF640BC | 3FF650BC | R/W |
| DMA configuration registers | ||||||
| SPI_DMA_CONF_REG | DMA configuration register | 3FF43100 | 3FF42100 | 3FF64100 | 3FF65100 | R/W |
| SPI_DMA_OUT_LINK_REG | DMA outlink address and configuration | 3FF43104 | 3FF42104 | 3FF64104 | 3FF65104 | R/W |
| SPI_DMA_IN_LINK_REG | DMA inlink address and configuration | 3FF43108 | 3FF42108 | 3FF64108 | 3FF65108 | R/W |
| SPI_DMA_STATUS_REG | DMA status | 3FF4310C | 3FF4210C | 3FF6410C | 3FF6510C | RO |
| SPI_IN_ERR_EOF_DES_ADDR_REG | Descriptor address where an error occurs | 3FF43120 | 3FF42120 | 3FF64120 | 3FF65120 | RO |
| SPI_IN_SUC_EOF_DES_ADDR_REG | Descriptor address where EOF occurs | 3FF43124 | 3FF42124 | 3FF64124 | 3FF65124 | RO |
| SPI_INLINK_DSCR_REG | Current descriptor pointer | 3FF43128 | 3FF42128 | 3FF64128 | 3FF65128 | RO |
| SPI_INLINK_DSCR_BF0_REG | Next descriptor data pointer | 3FF4312C | 3FF4212C | 3FF6412C | 3FF6512C | RO |
| SPI_INLINK_DSCR_BF1_REG | Current descriptor data pointer | 3FF43130 | 3FF42130 | 3FF64130 | 3FF65130 | RO |
| SPI_OUT_EOF_BFR_DES_ADDR_REG | Relative buffer address where EOF occurs | 3FF43134 | 3FF42134 | 3FF64134 | 3FF65134 | RO |
| SPI_OUT_EOF_DES_ADDR_REG | Descriptor address where EOF occurs | 3FF43138 | 3FF42138 | 3FF64138 | 3FF65138 | RO |
| SPI_OUTLINK_DSCR_REG | Current descriptor pointer | 3FF4313C | 3FF4213C | 3FF6413C | 3FF6513C | RO |
| SPI_OUTLINK_DSCR_BF0_REG | Next descriptor data pointer | 3FF43140 | 3FF42140 | 3FF64140 | 3FF65140 | RO |
| SPI_OUTLINK_DSCR_BF1_REG | Current descriptor data pointer | 3FF43144 | 3FF42144 | 3FF64144 | 3FF65144 | RO |
| SPI_DMA_RSTATUS_REG | DMA memory read status | 3FF43148 | 3FF42148 | 3FF64148 | 3FF65148 | RO |
| SPI_DMA_TSTATUS_REG | DMA memory write status | 3FF4314C | 3FF4214C | 3FF6414C | 3FF6514C | RO |
| DMA interrupt registers | ||||||
| SPI_DMA_INT_RAW_REG | Raw interrupt status | 3FF43114 | 3FF42114 | 3FF64114 | 3FF65114 | RO |
| SPI_DMA_INT_ST_REG | Masked interrupt status | 3FF43118 | 3FF42118 | 3FF64118 | 3FF65118 | RO |
| SPI_DMA_INT_ENA_REG | Interrupt enable bits | 3FF43110 | 3FF42110 | 3FF64110 | 3FF65110 | R/W |
| SPI_DMA_INT_CLR_REG | Interrupt clear bits | 3FF4311C | 3FF4211C | 3FF6411C | 3FF6511C | R/W |
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